The subject matter disclosed herein relates generally to the design of integrated circuits. More specifically, the disclosure provided herein relates to testing of integrated circuit designs.
Shrinking technology, along with increasing design density and frequency, has posed serious design and test challenges. One important issue of structural testing of integrated circuits in today's high-speed designs is the increasing number of types of timing-related defects and also dynamic and static voltage drops.
Among existing delay test models, the transition fault model is widely practiced in the industry to test delay-induced defects in integrated circuits. There are enhancements to these testing models which improve the quality of transition delay patterns; these enhancements are considered a cost-effective alternative to functional pattern generation. However, the at-speed launch and capture, and large number of switching events in the circuit during this transition delay testing may cause excessive peak power and large voltage drops.
The effect of these voltage drops have become increasingly more significant in recent years, as the effects during automatic test pattern generation (ATPG) pose design, test, and reliability challenges for chip manufacturers. This situation has grown more and more complicated with reductions in supply voltage and limitations on the further reduction of threshold voltages. As a result, the voltage drop may reduce cell noise immunity and may also lead to functional failures, in some cases.